Stacked microelectronic assemblies with central contacts

ABSTRACT

A stacked microelectronic assembly includes a dielectric element and a first and second microelectronic element stacked one on top of the other with the first microelectronic element underlying at least a portion of the second microelectronic element. The first microelectronic element and the second microelectronic element have front surfaces on which exposed on a central region of the front surface are contacts. A spacer layer may be provided under a portion of the second microelectronic element opposite a portion of the second microelectronic element overlying the first microelectronic element. Additionally, a third microelectronic element may be substituted in for the spacer layer so that the first microelectronic element and the third microelectronic element are underlying opposing sides of the second microelectronic element.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of the filing date of U.S.Provisional Patent Application No. 60/519,130 filed Nov. 12, 2003, thedisclosure of which is hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to stacked microelectronic assemblies andmethods of making such assemblies, to methods of forming such assembliesand to components useful in such assemblies.

Semiconductor chips are commonly provided as individual, prepackagedunits. A standard chip has a flat, rectangular body with a large frontface having contacts connected to the internal circuitry of the chip.Each individual chip typically is mounted in a package which, in turn,is mounted on a circuit panel such as a printed circuit board and whichconnects the contacts of the chip to conductors of the circuit panel. Inmany conventional designs, the chip package occupies an area of thecircuit panel considerably larger than the area of the chip itself. Asused in this disclosure with reference to a flat chip having a frontface, the “area of the chip” should be understood as referring to thearea of the front face. In “flip chip” designs, the front face of thechip confronts the face of the circuit panel and the contacts on thechip are bonded directly to the circuit panel by solder balls or otherconnecting elements. The “flip chip” design provides a relativelycompact arrangement; each chip occupies an area of the circuit panelequal to or slightly larger than the area of the chip's front face.However, this approach suffers from cost and reliability problems. Asdisclosed, for example, in certain embodiments of commonly-assigned U.S.Pat. Nos. 5,148,265; 5,148,266; and 5,679,977 the disclosures of whichare incorporated herein by reference.

Certain innovative mounting techniques offer compactness approaching orequal to that of conventional flip-chip bonding without the reliabilityand testing problems commonly encountered in that approach. Packageswhich can accommodate a single chip in an area of the circuit panelequal to or slightly larger than the area of the chip itself arecommonly referred to as “chip-sized packages.”

Besides minimizing the planar area of the circuit panel occupied bymicroelectronic assembly, it is also desirable to produce a chip packagethat presents a low, overall height or dimension perpendicular to theplane of the circuit panel. Such thin microelectronic packages allow forplacement of a circuit panel having the packages mounted therein inclose proximity to neighboring structures, thus producing the overallsize of the product incorporating the circuit panel. Various proposalshave been advanced for providing plural chips in a single package ormodule. In the conventional “multi-chip module”, the chips are mountedside-by-side on a single package substrate, which in turn can be mountedto the circuit panel. This approach offers only limited reduction in theaggregate area of the circuit panel occupied by the chips. The aggregatearea is still greater than the total surface area of the individualchips in the module.

It has also been proposed to package plural chips in a “stack”arrangement i.e., an arrangement where plural chips are placed one ontop of another. In a stacked arrangement, several chips can be mountedin an area of the circuit panel that is less than the total area of thechips. Certain stacked chip arrangements are disclosed, for example, incertain embodiments of the aforementioned U.S. Pat. Nos. 5,679,977 and5,148,265 patents, and U.S. Pat. No. 5,347,159, the disclosure of whichis incorporated herein by reference. U.S. Pat. No. 4,941,033, alsoincorporated herein by reference, discloses an arrangement in whichchips are stacked on top of another and interconnected with one anotherby conductors on so-called “wiring films” associated with the chips.

Despite these efforts in the art, further improvements would bedesirable in the case of multi-chip packages for chips having contactslocated substantially in central regions of the chips. Certainsemiconductor chips, such as some memory chips, are commonly made withthe contacts in one or two rows located substantially along a centralaxis of the chip.

SUMMARY OF THE INVENTION

One aspect of the present invention provides microelectronic assembliesincluding at least two microelectronic element elements having centralcontacts. A first microelectronic element faces downward and underlies aportion of the second microelectronic element. In the preferredembodiments, according to this aspect of the invention, the first andsecond microelectronic elements are provided with contacts located onfront surfaces on the microelectronic elements. The contacts aredisposed on a central region of the microelectronic elements. One orboth of the microelectronic elements are electrically connected toterminals on the dielectric elements. Apertures may be included with thedielectric elements wherein the apertures underlie central regions ofthe microelectronic elements so that the dielectric element does notobstruct the contacts on the microelectronic elements. In certain, morepreferred embodiments, terminals on the dielectric element are mobilerelative to the first and second microelectronic element elements. Incertain, more preferred embodiments, a spacer may be provided so as tounderlie a second portion of the second microelectronic element. Thespacer layer is placed on an opposing side of the second microelectronicelement as compared to the first microelectronic element with thecentral region of the second microelectronic element being locatedbetween the spacer and the first microelectronic element. An adhesivelayer may be used to connect the spacer layer or the firstmicroelectronic element or both to the second microelectronic element.

A stacked assembly, according to a further aspect of the presentinvention, includes a first microelectronic element, a secondmicroelectronic element and a third microelectronic element. Eachmicroelectronic element has contacts disposed on its front surface abouta central region of the element. The second microelectronic elementoverlies a portion of the first microelectronic element and the thirdmicroelectronic element; however, the central region of the secondmicroelectronic element is unencumbered by either of the two. The firstmicroelectronic element and the second microelectronic element may havesubstantially similar structures. As with the previous embodiment of thepresent invention, an adhesive layer may be provided so as to connectthe first and/or third microelectronic elements to the secondmicroelectronic element. A dielectric element may be provided so as tounderlie all of the microelectronic elements; however, apertures in thedielectric element are provided underlying central regions of themicroelectronic elements so as to not encumber contacts disposed onthese elements. As with the first embodiment of the present invention,wire leads connect the microelectronic elements to conductive featureslocated on the dielectric element. In either of the embodiments, wirebonds connecting contacts on the microelectronic elements to conductiveelements on the dielectric element may also take the form of wire leads,frangible leads, strip-like leads or the like.

A stacked assembly, according to even still a further aspect of thepresent invention, may include a first microelectronic element and asecond microelectronic element. Both microelectronic elements havingcontacts disposed along their central regions may be directly connectedto a circuit board or other microelectronic element via a mass ofconductive material. Examples of this massive conductive materialinclude solder, solder-core ball mass, a spring with solder fill, landssolder or the like. As is consistent with the stacked assemblies of thepresent invention, the second microelectronic element overlies at leasta portion of the first microelectronic element. A spacer layer may beprovided so as to underline a portion of the second microelectronicelement opposite the first microelectronic element. Furthermore, thespacer layer may take the form of a third microelectronic element alsobeing directly connected to a circuit board or the like.

In yet a still further aspect of the present invention, underlyingmicroelectronic elements, such as the first microelectronic element andthe third microelectronic element of any of the four describedassemblies, may include bond ribbons. Bond ribbons may be used forconnecting contacts disposed on the front surface of the microelectronicelements to terminals on the front surface of a dielectric element. Bondribbons may be connected to the contacts of the underlyingmicroelectronic elements and may be deformed to a vertical extensiveposition by moving the microelectronic elements and the dielectricelement away from one another.

As with all embodiments of the present invention, an encapsulantmaterial may be provided so as to cover and protect components of themicroelectronic elements.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic sectional elevational view of the stackedassembly according to a first embodiment of the present invention;

FIG. 2 is a bottom view of the stacked assembly according to a firstembodiment of the present invention;

FIG. 3 is a view similar to FIG. 1 but depicting another embodiment ofthe present invention;

FIG. 4 is a side view similar to FIG. 1 but depicting another embodimentof the present invention;

FIG. 5 is a block diagram side view depicting a basic design concept ofthe present invention; and

FIGS. 6, 7, and 8 are similar to FIG. 1 but depicting furtherembodiments of the present invention.

DETAILED DESCRIPTION

As shown in FIG. 1, a stacked microelectronic assembly 10 according toone embodiment of the present invention includes a first microelectronicelement 12 and a second microelectronic element 14. Microelectronicelement 12 has a front surface 16 and a back surface 18 opposite thefront surface 16. Microelectronic element 12 further includes centralregion 13 and first and second end regions 15 and 17, adjacent tocentral region 13. Electrical contacts 20 are exposed on front surface16. As used in this disclosure, a statement that a conductive featuresuch as a terminal, contact, bonding pad or the like is “exposed on” asurface or structure means that it is accessible to be electricallyconnected with another conductive element which approaches the surface.The conductive feature may be flush with the specified surface, mayproject outwardly from such surface, or may be recessed relative to suchsurface.

Contacts 20 on the first microelectronic element 12 are exposed withincentral region 13 of front surface 16. For example, contacts 20 may beformed as one or two parallel rows adjacent to the center of surface 16.Microelectronic element 14 is arranged similarly to microelectronicelement 12, in that it has a front surface 22, a back surface 24opposite the front surface and electrical contacts 26 are exposed on thefront surface 22. Microelectronic element 14 also includes a centralregion 19 and first and second end regions 21 and 23 adjacent to centralregion 19. In the first embodiment of the invention, as shown in FIG. 1,each microelectronic element 12 and 14 is a conventional semiconductorchip. Similarly, contacts 26 of second microelectronic element 14 aredisposed within central region 19 of front surface 22 and may also beformed as one or two parallel rows adjacent the center of front surface22.

The front surface 16 of the first microelectronic element facesdownwardly. Second microelectronic element 14 overlies firstmicroelectronic element 12 with the front surface 22 of the secondmicroelectronic element also facing downwardly. Front surface 22 ofsecond microelectronic element 14 and back surface 18 of firstmicroelectronic element 12 confront each other in a “front-to-back”configuration. With regard to the present disclosure, terms such as“downwardly” or “upwardly” are used to describe directions that areopposed to each other without regard to any gravitational frame ofreference. Similarly, terms such as “over” and “under”, or “above” and“below” are used to describe the relative position to elements orassembly within the frame of reference of the assembly itself.

Second end region 23 of microelectronic element 14 overlies first endregion 15 of microelectronic element 12. The actual percentage ofmicroelectronic element 14 which overlies microelectronic element 12 isnot important but what is important is that the portion of front surface22 of microelectronic element 14 which has disposed within in itcontacts 26, i.e. central region 19, does not overlie microelectronicelement 12. Thus specific dimensions of central region 19 and first andsecond end regions 21 and 23 may fluctuate depending on where and howmany contacts 26 are disposed on front surface 22. Furthermore, asufficient area of front surface 22 should overlie microelectronicelement 12 so as to support microelectronic element 14.

The assembly also includes a dielectric element 30 having a firstsurface 32 and a second surface 34 with electrically conductiveterminals 36 exposed on second surface 34. Dielectric element 30includes aperture 33 located substantially under central region 13 ofmicroelectronic element 12 so as not to obstruct contacts 20.Microelectronic element 12 is disposed over first surface 32 ofdielectric element 30 in a downwardly-facing orientation with frontsurface 16 confronting upwardly-facing first surface 32. Preferably,dielectric element 30 comprises a layer of flexible material, such as alayer of polyimide, BT resin or other dielectric material of the typecommonly utilized for making tape automated bonding (“TAB”) tapes, or arelatively rigid, board-like material such as a thick layer offiber-reinforced epoxy as, for example, an Fr-4 or Fr-5 board and alayer of a die attach adhesive 31 defining the first surface 32.Dielectric element 30 also includes additional conductive featuresincluding bond pads 40 exposed on second surface 34 and conductivetraces 42 connecting bond pads 40 to terminals 36.

As shown in FIGS. 1 and 2, leads 50 are in the form of wire bonds, andare used to connect contacts 20 of first microelectronic element 12 tosome of the bond pads 40. Other leads in the form of wire bonds 70 areused to connect contacts 26 of second microelectronic element 14 toother bond pads 40. The dielectric element may further include asolder-mask layer 52 defining the second surface 34, with apertures orholes at bond pads 40. Preferably, at least some of the wire bonds 50,70 are connected through bond pads 40 and traces 42 to at least some ofthe terminals 36.

Most preferably, all of the conductive features on the dielectricelement are formed from a single layer of metal. This avoids the needfor precise registration between multiple layers of metallic featuresand formation of interconnections between such layers during manufactureof the dielectric element. Additional metallic features (not shown) suchas conductive planes for use as ground planes or power distributionplanes may be provided.

An adhesive layer 60 may connect microelectronic elements 12 and 14.Adhesive layer 60 may be a die-attach adhesive, and may be comprised oflow elastic modulus material such as a silicone elastomer. However,where the two microelectronic elements are conventional semiconductorchips formed from the same material, they will tend to expand andcontract in unison in response to temperature changes and, accordingly,a relatively rigid attachment as, for example, a thin layer of a highelastic modulus adhesive or solder can be employed.

As illustrated in FIG. 1, at least some of the terminals 36 are disposedbeneath front surface 16 of microelectronic element 12. At least some ofthe terminals 36 are movable with respect to the first electronicelement 12 and hence with respect to at least some of contacts 20.

Assembly 10 may further include an encapsulant 80 that covers leads 50,70 and protects the microelectronic elements 12, 14. The encapsulant mayalso be provided between the front surfaces 16, 22 and the first surface32, thoroughly surrounding leads 50, 70, and may fill open spacesbetween microelectronic elements 12 and 14. Preferred encapsulantscomprise flexibilized epoxies or silicone elastomers.

Assembly 10 may further include a plurality of joining units, such aseutectic solder balls 81, as shown in FIG. 1. Solder balls 81 areattached to terminals 36 and hence are electrically interconnected to atleast some of the bond pads 40, leads 50 and 70 and contacts 20 and 26.Other types of joining units such as solid-core solid balls or masses orballs of a diffusion-bonding or eutectic bonding alloy, masses ofconductive polymer composition, or the like may be employed. In use, theassembly is mounted on a circuit panel such as circuit board 95 havingcontact pads 94. The second surface 34 of the dielectric element 30faces downwardly towards the circuit board, and solder balls 81 arebonded to the contact pads of the circuit board, thus connecting thecontact pads to the microelectronic elements. The contact pads on thecircuit board are connected by traces on or in the circuit board to theother elements of an electrical circuit which must co-act withmicroelectronic elements 12 and 14. During the bonding operation, andduring operation of the completed circuit board and circuit,differential thermal expansion and contraction of the circuit board andchips may occur. This may be caused by the difference between thecoefficient of expansion of the microelectronic elements and circuitboard; by difference in temperature between the microelectronic elementsand the circuit board; or by combinations of these factors. Suchdifferential thermal expansion causes some or all of the contact pads 95to move relative to the microelectronic element and contacts 20 and 26.Desirably, movement of terminals 36 relative to microelectronic elementsrelieves some or all of the stress which would otherwise be imposed onsolder balls 81 by relative movement of the terminals and contact pads.To enhance moveability of terminals 36 relative to the microelectronicelements, dielectric element 30 may include a compliant layer. Forexample, die attach adhesive 31 may be a compliant die attach adhesive.Additionally, movement of terminals allows for easier testability. Thisis due to the fact that if either terminals 36 or contact pads locatedon a tester are not in exact planer alignment, terminals 36 aresufficiently flexible so as to be able to align most terminals with acorresponding contact pad. In other words, movement of terminals 36enhance the engageability of a test fixture to the microelectronicassembly.

Preferred combinations of the features described above allow themanufacture of a two-chip center stack assembly having a thickness ofless than 1.2 mm above the terminals 36. More preferably, such athickness will be 0.7 mm (700 microns) or less.

In preferred embodiments of the present invention, joining units orsolder balls 81 have a height of about 300 microns or less; morepreferably, about 200 microns or less, and most preferably about 100microns or less. Thus the overall height of the assembly above thecircuit panel after assembly, including the height of the joining units,most preferably is about 1.5 mm or less, and most preferably about 1.3mm or less. Joining units having such low heights, also know as “finepitch” joining units, may be used to beneficially affect the assemblieswherein the terminals are moveable with respect to the microelectronicelements and relative to the contacts on the microelectronic elements.As discussed above, this moveability relieves the mechanical strain ordeformation generated by differential thermal expansion of themicroelectronic elements. Some of the deformation may also be relievedby flexure of the joining units connecting the assembly to a circuitpanel, such as a printed circuit board. Larger joining units can flex toa greater extent than smaller ones and, therefore, relieve a greateramount of deformation without failure due to fatigue of the joiningunits. In preferred embodiments of the present invention, the movementof the terminals relative to microelectronic elements relieves asignificant portion of such deformation, allowing the use of relativelysmall joining units while still maintaining acceptable levels ofreliability. However, moveability is not essential in all embodiments.

An alternate embodiment of the present invention is shown in FIG. 3.Microelectronic assembly 100 is similar to microelectronic elementassembly 10 but also includes a spacer layer 164 disposed beneath firstend region 121 of second microelectronic element 114 and may overlay aportion of dielectric element 130. Also, dielectric element 130 includesa second aperture aligned with the central region of the secondmicroelectronic element. Spacer layer 164 is designed to balance andsupport microelectronic element 114 in conjunction with microelectronicelement 112. Desirably, spacer layer 164 is made of a compliant materialthat allows movement of dielectric element 130, and hence movement ofterminals 136, relative to contacts 120 and 126. Preferred materials forsuch compliant layers include epoxies and silicones, with flexibilizedepoxies and silicone elastomers being particularly preferred. The leads150, 170 are flexible to permit such movement.

Encapsulant 180 may be provided so as to protect and seal assembly 100,similar to assembly 10. In addition, in embodiments that do not includea separate spacer layer 164, the encapsulant may also be providedbetween the front surfaces 116, 122 and the first surface 132,thoroughly surrounding leads 150, 170, and may fill open spaces betweenmicroelectronic elements 112 and 114.

It is preferred, although not necessary to the invention, thatmicroelectronic elements 112 and 114 are attached to each other by meanssuch as adhesive layer 160. It is also preferred that microelectronicelement 114 and spacer layer 164 are attached to each other by adhesivelayer 160.

In a third embodiment shown in FIG. 4, assembly 200 includes a thirdmicroelectronic element 202, along with first and second microelectronicelements 212, 214. Third microelectronic element 202 includes frontsurface 203, rear surface 204, central region 205 and first and secondend regions 206 and 207. Electrical contacts 208 are disposed on frontsurface 203. Assembly 200 may be substantially similar to assembly 100discussed above with reference to FIG. 3. The one significant differenceis that microelectronic element 202 replaces spacer layer 164 underlyingmicroelectronic element 214. Specifically, second end region 207 ofmicroelectronic element 202 underlies first end region 221 ofmicroelectronic element 214. Consistent with the first embodiment of thepresent invention, the percentage of front surface 222 overlyingmicroelectronic element 202 may fluctuate depending on the number ofcontacts 226 located on front surface 222 of microelectronic element214. In other words central region 219 of microelectronic element 214must not overlie second end region 207 of microelectronic element 202.However, the amount of front surface 222 of microelectronic element 214overlying second end region 207 of microelectronic element 202 should besufficient to support microelectronic element 214 in conjunction withmicroelectronic element 212.

Similar to microelectronic 12 of FIG. 1, contacts 208 disposed on frontsurface 203 of microelectronic element 202 have wire bonds 250 in theform of leads for connecting contacts 208 to bond pads 240 of dielectricelement 230. Dielectric element 230 may include solder mass layer 252defining second surface 234 of dielectric element 230 with apertures orholes at bond pads 240. Dielectric element 230 can be seen as just alarger version of dielectric element 30 of assembly 10. Apertures 233are provided in dielectric element 230 so that dielectric element 230does not obstruct leads 250 or 270. The apertures are aligned with thecentral regions of each microelectronic element. Traces 242 connect thevarious conductive features to each other, as discussed in conjunctionwith the first embodiment of the present invention. Similarly, at leastsome of the leads 250 and 270 associated with microelectronic elements202, 212 and 214 are connected to at least some of the terminals 236,whereas at least some bond pads 240 are also connected to at least someof the terminals 236. Some or all of the bonds pads 240 may be connectedwith some or all of the leads 250 and 270. Assembly 200 may furtherinclude an encapsulant 280 that covers the leads 250, and 270 andprotects the microelectronic element 212, 214 and 202. Encapsulant 280is similar to encapsulant 80 and can be employed for similar purposes.

The assembly 200 can be thought of as a brick wall having an A-B-Aconfiguration wherein A designates a lower tier element such as firstmicroelectronic element 212 or third microelectronic element 202, and Bdesignates an upper tier microelectronic element such as secondmicroelectronic element 214, and with the contact-bearing centralregions arranged in the order indicated. Each upper tier element Boverlies a portion of at least one lower tier element A and A′ so as toform the structure shown in FIG. 4.

As shown in FIG. 5, a third embodiment of the invention makes use of theA-B-A configuration by continuing the structure horizontally outwards.FIG. 5 is a skeletal depiction of a B-A-B-A-B configuration. Thestructure may have a configuration of A-B-A-B-A or A-B-A-B or B-A-B-A-B,or any other combination of the two where a structure A and a structureB are adjacent to one another. These structures could be extended outindefinitely until a required amount of microelectronics elements aremet. Additionally, structures that follow varying designs such as havinga plurality of A structures adjacent to one another without an overlyingB structure may be employed.

In an alternate embodiment of the present invention as shown in FIG. 6,assembly 300 includes microelectronic elements denoted by the structureA altered so as to include a substantially continuous dielectric element330 underlying at least one microelectronic element denoted A. For thisdiscussion microelectronic element 312 will represent microelectronicelements having a structure equal to A. Contacts 320 are electricallyconnected to bond ribbons leads 390. The bond ribbons may be of the typedescribed in U.S. Pat. No. 5,518,964, the disclosure of which isincorporated by reference herein. As disclosed in certain embodiments ofthe '964 patent, the bond ribbons may be initially formed in place onthe first surface of the dielectric element, and may initially extend inthe plane of such surface. The bond ribbons may be connected to thecontacts 320 of the first microelectronic element 312 and may bedeformed to the vertical-extensive position depicted in FIG. 6 by movingthe first microelectronic element 312 and the dielectric element 330away from one another after bonding the ribbons to the contacts of thefirst microelectronic element. Related bond ribbon configurations andmethods of forming bond ribbons embodiments are discussed in U.S. Pat.Nos. 6,329,607; 6,228,686; 6,191,368; 5,976,913; and 5,859,472, thedisclosures of which are also incorporated by reference herein.

In a further alternate embodiment as shown in FIG. 7, assembly 400includes first microelectronic element 412 and second microelectronicelement 414. The microelectronic elements in assembly 400 may besubstantially similar to the first and second microelectronic elementsemployed with assembly 10 of FIG. 1. However, assembly 400 differs fromthe previous assemblies in that the dielectric layer has not beenincluded in the assembly. Additionally, masses of conductive material,preferably solder balls 481, are employed for conductively connectingcontacts 420 of first microelectronic element 412 to the circuit board.Similar masses 483 connect contacts 426 of second microelectronicelement 414 directly to contacts 494 of circuit board 495. In themounted condition illustrated in FIG. 7, the masses 481 associated withthe contacts 420 of the first microelectronic element have a lesserheight than masses 483 associated with the second microelectronicelement. Additionally, the conductive material may be comprised of othermaterial as, for example, polymeric conductive materials, solid coresolder balls, solder filled springs, solder land or the like. Acombination of options may also be employed. As with all the previousembodiments, an adhesive layer (not shown) may connect microelectronicelements 412 and 414. Additionally, an encapsulant (also not shown) aswith all embodiments of the present invention may be included withassembly 400. Although the elimination of the dielectric layer has beendescribed with specific reference to assembly 400, the dielectric layermay be also eliminated from other embodiments described herein.Additionally, conductively connecting contacts on microelectronicelements directly to contacts on a circuit board, as shown in FIG. 7,may be incorporated with other embodiments described within the presentapplication.

The embodiment shown in FIG. 7 may be assembled using various methods.For example, microelectronic element 412 may be preassembled tomicroelectronic element 414. The entire assembly may then be surfacemounted to circuit board 495 using solder balls 481 with standardsurface mount techniques known in the art. Additionally, microelectronicelement 412 may be surface mounted to circuit board 495 first and in anext step, microelectronic element 414 is surface mounted to the circuitboard.

FIG. 8 shows assembly 500 employing alternate conducting leadsconnecting contacts 520 and 526 to other conductive features of theassembly. Assembly 500 may include any or all of the features previouslydescribed in this reference herein in conjunction with other embodimentsof the present invention. The one significant modification to assembly500 is that strip-like leads 550 formed integrally with traces 542 areused to connect contacts 520 and 526 to conductive features of themicroelectronic elements. The construction of such strip-like leads isdescribed, for example, in commonly assigned U.S. Pat. No. 5,915,752,which is hereby incorporated by reference herein. As shown in FIG. 8,assembly 500 may include a spacer layer 564 underlying secondmicroelectronic element 514. As with all embodiments of the presentinvention, spacer layer 564 may be made of a compliant material oradditionally, spacer layer 564 may be comprised of a smallmicroelectronic element. In the case where spacer layer 564 is a smallmicroelectronic element, the small microelectronic element may eithernot extend horizontally past second microelectronic element 514 or onlyextend slightly past the edge of microelectronic element 514. Variousadhesive layers and encapsulants may be included with assembly 500, asdescribed throughout this disclosure.

Although the invention herein has been described with reference toparticular embodiments, it is to be understood that these embodimentsare merely illustrative of the principles and applications of thepresent invention. It is therefore to be understood that numerousmodifications may be made to the illustrative embodiments and that otherarrangements may be devised without departing from the spirit and scopeof the present invention as defined by the appended claims.

The invention claimed is:
 1. A microelectronic assembly comprising: adielectric element having an upwardly-facing first surface and adownwardly-facing second surface and having, terminals exposed at saidsecond surface, a first aperture, and a second aperture; a firstmicroelectronic element overlying said dielectric element, the firstmicroelectronic element having an upwardly-facing rear surface and adownwardly-facing front surface and having contacts exposed at saidfront surface; and a second microelectronic element having anupwardly-facing rear surface and a downwardly-facing front surface,having contacts exposed at said front surface, said front surface ofsaid second microelectronic element including a central region and afirst and second end region regions on opposite sides of said centralregion, said contacts of said second microelectronic element beingdisposed in said central region and facing downwardly toward saiddielectric element, said first side end region overlying said firstmicroelectronic element, said central region and said second side endregion projecting outwardly from said first microelectronic element,said first aperture underlying said contacts of said firstmicroelectronic element, said second aperture underlying said contactsof said second microelectronic element, wherein said first and secondmicroelectronic elements are electrically connected with said terminals.2. The microelectronic assembly of claim 1, wherein said firstmicroelectronic element has a central region and a first and second sideregion, said contacts of said first microelectronic element beingdisposed within said central region of said first microelectronicelement.
 3. The microelectronic assembly of claim 1, wherein saiddielectric element includes at least one aperture, said aperturesubstantially underlying said contacts of said front surface of saidfirst microelectronic element.
 4. The microelectronic assembly of claim1, wherein said dielectric element includes at least one aperture, saidaperture substantially underlying said contacts of said front surface ofsaid second microelectronic element.
 5. The microelectronic assembly ofclaim 1, further comprising a spacer layer, wherein said second side endregion of said second microelectronic element overlies said spacerlayer.
 6. The microelectronic assembly of claim 1, further comprising athird microelectronic element, wherein said second side end region ofsaid second microelectronic element overlies said third microelectronicelement.
 7. The microelectronic assembly of claim 6, further comprisingan adhesive layer, wherein said adhesive layer connects said firstmicroelectronic element and said third microelectronic element to saidsecond microelectronic element.
 8. The microelectronic assembly of claim2, further comprising a third microelectronic element, wherein saidsecond end region of said second microelectronic element overlies saidthird microelectronic element.
 9. The microelectronic assembly of claim8, wherein said third microelectronic element is substantially similarto said first microelectronic element.
 10. The microelectronic assemblyof claim 9, wherein said dielectric element underlies at least a portionof said third microelectronic element.
 11. The microelectronic assemblyof claim 1, further comprising a first encapsulant material, whereinsaid first encapsulant material is disposed in contact with said firstmicroelectronic element and said second microelectronic element.
 12. Themicroelectronic assembly of claim 6, further comprising a firstencapsulant material, wherein said first encapsulant material isdisposed in contact with said first microelectronic element, said secondmicroelectronic element and said third microelectronic element.
 13. Themicroelectronic assembly of claim 1, further comprising an adhesivelayer, wherein said adhesive layer connects said first microelectronicelement to said second microelectronic element.
 14. The microelectronicassembly of claim 1, further comprising wire leads, wherein said firstand second microelectronic elements are electrically connected with saidterminals via said wire leads.
 15. The microelectronic assembly of claim1, further comprising traces on said dielectric element connected tosaid terminals and leads integral with said traces, wherein said firstand second microelectronic elements are electrically connected with saidterminals via said leads.
 16. A microelectronic assembly comprising: adielectric element having an upwardly-facing first surface and adownwardly-facing second surface and having terminals exposed at saidsecond surface; a first microelectronic element having anupwardly-facing rear surface and a downwardly-facing front surface andhaving contacts exposed at said front surface; and a secondmicroelectronic element having an upwardly-facing rear surface and adownwardly-facing front surface, having contacts exposed at said frontsurface, said front surface of said second microelectronic elementincluding a central region and a first and second region on oppositesides of said central region, said contacts of said secondmicroelectronic element being disposed in said central region, furtherwherein said first side region overlies said first microelectronicelement, said central region and said second side region projectingoutwardly from said first microelectronic element wherein said first andsecond microelectronic elements are electrically connected with saidterminals.
 17. A microelectronic assembly comprising: a firstmicroelectronic element having an upwardly-facing rear surface and adownwardly-facing front surface and having contacts exposed at saidfront surface; and a second microelectronic element having anupwardly-facing rear surface and a downwardly-facing front surface,having contacts exposed at said front surface, said front surface ofsaid second microelectronic element including a central region and afirst and second end region on opposite sides of said central region,said contacts of said second microelectronic element being disposed insaid central region, said first side region overlying said firstmicroelectronic element, said central region and said second side regionprojecting outwardly from said first microelectronic element.
 18. Themicroelectronic assembly of claim 17, wherein said first microelectronicelement has a central region and a first and second side region, saidcontacts of said first microelectronic element being disposed in saidcentral region of said first microelectronic element.
 19. Themicroelectronic assembly of claim 17, further comprising a spacer layer,wherein said second side region of said second microelectronic elementis overlying said spacer layer.
 20. The microelectronic assembly ofclaim 17, further comprising a third microelectronic element, whereinsaid second side region of said second microelectronic element isoverlying said third microelectronic element.
 21. The microelectronicassembly of claim 18, further comprising a third microelectronicelement, wherein said second region of said second microelectronicelement overlies said third microelectronic element.
 22. Themicroelectronic assembly of claim 20, wherein said third microelectronicelement is substantially similar to said first microelectronic element.23. The microelectronic assembly of claim 17, further comprising a firstencapsulant material, wherein said first encapsulant material isdisposed in contact with said first microelectronic element and saidsecond microelectronic element.
 24. The microelectronic assembly ofclaim 17, further including an adhesive layer, wherein said adhesivelayer connects said first microelectronic element to said secondmicroelectronic element.
 25. The microelectronic assembly of claim 20,further comprising an adhesive layer, wherein said adhesive layerconnects said first microelectronic element and said thirdmicroelectronic element to said second microelectronic element.
 26. Themicroelectronic assembly of claim 17, further comprising a circuit boardand masses of conductive material, said masses of conductive materialconnecting said contacts of said first microelectronic element and saidcontacts of said second microelectronic element to said circuit board.27. The microelectronic element assembly of claim 26, wherein saidconductive material includes solder.
 28. The microelectronic assembly ofclaim 1, wherein said dielectric element includes a first intermediateportion disposed between said first and second apertures, and saidterminals include intermediate terminals disposed on said firstintermediate portion.
 29. The microelectronic assembly of claim 28further comprising a third microelectronic element overlying saiddielectric element, wherein said second end region of said secondmicroelectronic element overlies said third microelectronic element. 30.The microelectronic assembly of claim 28 wherein said thirdmicroelectronic element has an upwardly-facing rear surface, adownwardly-facing front surface and contacts exposed at the frontsurface of the third microelectronic element.
 31. The microelectronicassembly of claim 30 wherein said dielectric element includes a thirdaperture underlying said contacts of said third microelectronic element.32. The microelectronic assembly of claim 31 wherein said dielectricelement includes a second intermediate portion disposed between saidsecond and third apertures and said terminals include secondintermediate terminals disposed on said second intermediate portion. 33.The microelectronic assembly of claim 1, further comprising leadsextending through said apertures, said contacts being connected to saidterminals via said leads.
 34. The microelectronic assembly of claim 33,wherein said leads include first leads extending through said firstaperture to said contacts of said first microelectronic element andsecond leads extending through said second aperture to said contacts ofsaid second microelectronic element.
 35. The microelectronic assembly ofclaim 33 wherein said dielectric element includes bond pads exposed atsaid second surface and electrically connected to said terminals, andsaid leads include wire bonds extending through said apertures from saidcontacts to said bond pads.
 36. The microelectronic assembly of claim33, wherein said dielectric element includes a first intermediateportion disposed between said first and second apertures and saidterminals include first intermediate terminals disposed on said firstintermediate portion.
 37. The microelectronic assembly of claim 36,wherein said leads include first leads extending through said firstaperture to said contacts of said first microelectronic element andsecond leads extending through said second aperture to said contacts ofsaid second microelectronic element.